As shown in FIG. 1, a conventional address input buffer, e.g., of an SRAM or a DRAM, receives a desired memory address location signal AI and, internally to the memory device, transmits an address location signal AO. The conventional input buffer includes: a second PMOS transistor P2 the source of which is connected to an external voltage Vcc and the gate of which is connected to an output of an inverter IN1; a first PMOS transistor P1 the source of which is connected to the drain of the second PMOS transistor P2, the drain of first PMOS transistor being connected to an output terminal OUT and the gate of which is connected to an input terminal IN; a first NMOS transistor N1 the drain of which is connected to the output terminal OUT, the source of which is connected to a ground voltage Vss and the gate of which is connected to the input terminal N1; an inverter IN1 for receiving a chip enable signal CE; and a second NMOS transistor N2 the drain of which is connected to an output terminal OUT, the gate of which is connected to the inverter IN1 and the source of which is connected to the ground voltage Vss.
With reference to FIGS. 1 through 4, the operation of the conventional input buffer will now be described.
When the chip enable signal CE is at a high potential, the output value of the inverter N1 becomes a low potential so that the second PMOS transistor P2 is turned on and the second NMOS transistor N2 is turned off. With the chip enable CE signal high, it is possible for current to flow through the conventional input buffer from the external high potential Vcc to the ground potential Vss depending upon the state of the signal AI. This current is known as Iss.
As shown in FIG. 2, when the input signal AI is at a high potential(and the chip enable signal CE is high), the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on so that an output signal AO becomes a low potential.
To the contrary, when the input signal AI is at a low potential, the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off so that output signal AO becomes a high potential.
When the chip enable signal CE is at a low potential, i.e.) in standby mode, the output value of the inverter N1 remains at a high potential so that the second PMOS transistor P2 is turned off and the second NMOS transistor N2 is turned on. Accordingly, the output signal AO remains at a low potential irrespective of the level of the input signal AI. Also, no current Iss will flow through the conventional input buffer from the external high potential Vcc to the ground potential Vss.
In FIG. 2, during the concurrent transitions of AI and AO from Vss to Vcc and from Vcc to Vss, respectively, there occurs a value of AI, namely the middle voltage or Vm, that will cause both the PMOS P1 and NMOS N1 transistors to turn on. This middle voltage corresponds to the intersection of the AI and AO voltage curves. The value of Vm depends upon the particular characteristics of the transistors involved and their collective configuration. Where Vcc=5 volts and Vss=0 volts, a typical value of Vm is about 1.5 volts. The current Iss peaks at Vm. A similar phenomenon occurs when the signals AI and AO concurrently transition from Vcc to Vss and from Vss to Vcc, respectively. As depicted in FIG. 3, however, the latter type of transitions are of much less consequence than the former transitions, i.e., much more current is consumed when AI goes high and AO goes low.
As shown in FIG. 4, when a middle voltage of about 1.5V is applied as the input signal AI, the first PMOS transistor P1 and the first NMOS transistor N1 are both turned on, resulting in an increased power consumption due to a significant peak in the current waveform Iss.
Again, as shown in FIG. 3, when the input signal AI goes from a low potential to a high potential or vice versa, a peak in the current Iss occurs. These peaks in Iss generate noise because the Vss level is momentarily raised. This noise can cause the chip to malfunction.